By Gracieli Posser,Sachin S. Sapatnekar,Ricardo Reis
This publication describes new and powerful methodologies for modeling, studying and mitigating cell-internal sign electromigration in nanoCMOS, with major circuit lifetime advancements and no effect on functionality, region and gear. The authors are the 1st to research and suggest an answer for the electromigration results inside of common sense cells of a circuit. They express during this e-book that an interconnect within a mobilephone can fail decreasing significantly the circuit lifetime and so they exhibit a strategy to optimize the life of circuits, via putting the output, Vdd and Vss pin of the cells within the much less serious areas, the place the electromigration results are diminished. Readers may be enabled to use this technique just for the severe cells within the circuit, warding off impression within the circuit hold up, sector and function, hence expanding the life of the circuit with no loss in different characteristics.
Read or Download Electromigration Inside Logic Cells: Modeling, Analyzing and Mitigating Signal Electromigration in NanoCMOS PDF
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Additional resources for Electromigration Inside Logic Cells: Modeling, Analyzing and Mitigating Signal Electromigration in NanoCMOS
Electromigration Inside Logic Cells: Modeling, Analyzing and Mitigating Signal Electromigration in NanoCMOS by Gracieli Posser,Sachin S. Sapatnekar,Ricardo Reis